Editing Openai/69676758-d944-8003-a3d4-835e33b4e372 (section)

=== Assistant: Understood. ===
Understood. You are asking for the actual hardware / interconnect chain, not the logical graphics stack.

Here is the correct end-to-end picture, from CPU outward, with the important caveats.

==== ### ====
* Executes application code
* Submits rendering commands (draw calls, compute, copies)

⬇

===== - Command buffers, resources, sometimes framebuffers =====
* Shared via DMA, not copied per frame

⬇

===== - General-purpose, packet-switched interconnect =====
* Used for: - Command submission - Resource uploads - Synchronization
* Not used to transmit live pixel streams

⬇

===== Inside the GPU, things split: =====

====== - Execute shaders ======
* Produce rendered images into VRAM

====== - Reads finished framebuffers from VRAM ======
* Applies timing, scaling, color conversion
* Generates a pixel stream

⬇

===== - Dedicated hardware block on the GPU =====
* Converts pixel stream into: - DisplayPort packets - Electrical signaling on DP lanes
* Completely independent of PCIe

⬇

===== - Monitor decodes DP packets =====
* Drives the panel timing controller (TCON)

==== DisplayPort is NOT “on top of PCIe.” ====
* PCIe is used to control the GPU and move data into VRAM
* DisplayPort is a separate hardware output path
* They meet only inside the GPU silicon

Think of the GPU as having:
* A PCIe endpoint on one side
* One or more display PHYs on the other

==== Slightly different wiring: ====
* CPU + GPU are on the same die
* Framebuffer lives in system RAM
* Display engine reads RAM directly
* DP PHY may be: - On the CPU package, or - On the motherboard chipset via internal links

Still:
* No PCIe in the display path
* PCIe is only for external GPUs or devices

==== ### ====
* DP is tunneled, not layered: - Raw DP packets are multiplexed over the cable - Still generated by the same DP display engine
* PCIe tunneling is a separate logical channel

===== - If pixels go over PCIe or network, it is no longer DisplayPort =====
* It becomes a framebuffer copy + software protocol

==== DisplayPort is generated by the GPU’s display controller and leaves the GPU through a dedicated PHY; PCIe only feeds the GPU, it does not carry the display signal. ====

If you want, I can also explain this from a die-level block diagram perspective or compare it to how NVLink or SoC display paths work.