Editing Openai/6956b4b2-0c24-8012-ac81-f0ad62b8cc3e (section)

=== Assistant: That statement is not correct — DDR5 does not use HBM. ===
That statement is not correct — DDR5 does not use HBM. They are completely different memory technologies. I’ll keep this clear and technical.

==== ### ====
* Discrete DRAM chips on DIMMs or soldered packages
* Connected to the CPU via memory channels
* Bandwidth: ~40–80 GB/s per channel
* Latency: optimized for general-purpose computing
* Packaging: standard DRAM packages (TSOP/BGA)
* Used in: PCs, laptops, servers, consoles

===== - 3D-stacked DRAM (multiple dies stacked vertically) =====
* Connected via silicon interposer directly next to the GPU
* Bandwidth: 800 GB/s → 3 TB/s+
* Latency: optimized for massive parallel access
* Packaging: advanced CoWoS / interposer tech
* Used in: AI accelerators, HPC GPUs

==== - Both are made by the same companies (Samsung, SK Hynix, Micron) ====
* Both are “DRAM”
'' Some CPUs use HBM ''alongside* DDR5 (rare, server/HPC only)
* Marketing articles sometimes say “AI uses DRAM” without distinction

But:

: 

==== Even though they’re different: ====
* HBM uses far more silicon per GB
* It consumes advanced packaging capacity
* That’s why HBM can be constrained while DDR5 is not

DDR5 manufacturing is high-volume and mature. HBM is low-volume and packaging-limited.

==== - ❌ DDR5 does not use HBM ====
* ❌ AI is not draining DDR5 supplies
* ✅ HBM shortages affect AI GPU availability, not PC RAM

If you want, I can explain this at the chip-layout / manufacturing level or show why Apple’s unified memory is still not HBM.